module SR(CLK,S,NS,Rst);
input CLK,Rst;
input [5:0] NS;
output reg[5:0] S ;
always@(posedge CLK) begin
    if(Rst) begin
    S<=6'b000000;
    end
    else 
    S=NS;
    end
    initial begin
        S=6'b000000;
    end
    endmodule